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MOReal

by Suitera · Since 2020
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ActiveAvailable globallyCloud
Quick facts
VendorSuitera
Year launched2020
StatusActive
Location5834 Westslope Dr, Austin, TX, 78731
Countries servedGlobal
Languages1
Integrations
Free tier
Free trial
Contact salesYES

About MOReal

MOReal is a collaborative software platform from Suitera that provides tools for managing remote teams. It offers features such as real-time collaboration, project tracking, and team communication, so users can stay connected and on task. The platform is designed to facilitate efficient teamwork regardless of location. MOReal includes integration with popular productivity tools, customizable workflows, and reporting functionalities to assist in project management. Key capabilities: real-time collaboration project tracking team communication integration with productivity tools customizable workflows Best for: remote teams that need effective communication and project management solutions.

MOReal™ by Suitera is a highly specialized engineering software that addresses one of the most difficult challenges in modern semiconductor design: the simulation of extremely large post-layout parasitic netlists. After parasitic extraction, integrated circuits—especially at advanced nodes—produce electromagnetic models containing millions of elements, often making traditional SPICE simulators slow or completely impractical. MOReal™ functions as an intelligent intermediary in the EDA workflow, applying advanced model order reduction algorithms to compress these massive netlists into much smaller, mathematically equivalent circuits. The tool delivers exceptional performance, achieving reduction ratios of up to 1000 times while preserving physical integrity through guaranteed passivity and realizability. Its massively parallel processing architecture allows engineers to scale computation across multiple cores or cloud servers, producing near-linear speed improvements as resources increase. Another important strength is its memory efficiency, which enables the software to process netlist files larger than the available system RAM—an ability that is critical for handling real-world industrial designs. MOReal™ supports a wide spectrum of parasitic representations including R, RC, RCC, RLC, and RLCK models, and operates across customizable frequency ranges from DC to terahertz.

Pros & Cons

What users like
  • +Unmatched speed achieved through parallel processing and advanced conditioning.
  • +Highly memory-efficient design allows processing of files much larger than the available system RAM.
  • +Maintains accuracy with pre-specified error margins, ensuring high-fidelity results in simulations.
What users flag
  • Steep learning curve requires deep understanding of IC design flows and related technical expertise.
  • Specialized usage limits applicability to linear parasitic networks and excludes non-linear active devices entirely.

Features

Key features

High-Ratio Netlist Reduction
Achieves a massive reduction ratio of up to 1000x or 95%, transforming gigantic parasitic networks into compact circuits.
Massively Parallel Algorithm
Features a computational design that provides near-linear speedup as more CPU resources are added for extremely fast processing.
Conditioning Enhancement
Optimizes the mathematical conditioning of the reduced circuit, which drastically decreases the time iterative solvers take during SPICE simulations.
Memory-Optimized Execution
Employs advanced techniques that allow the tool to process netlist files larger than the physical memory available on the hosting node.
Guaranteed Passive Realizability
Produces reduced netlists that are guaranteed to be passive and composed of physical RLC components, ensuring stability in any simulator.
Frequency-Agile Reduction Modes
Supports both narrowband and wideband extraction types, maintaining accuracy from DC levels up to the terahertz range.

Additional features

Model Order Reduction (MOR)
Applies novel mathematical algorithms to reduce the complexity of linear parasitic networks while preserving original circuit behavior.
High Reduction Ratio
Enables a reduction of parasitic nodes and elements by more than 95%, making massive netlists manageable for simulation.
Accuracy Preservation
Utilizes a smart algorithm to maintain a pre-specified error margin relative to the original parasitic network.
Memory Optimization
Allows the reduction of gigantic netlists on machines with low memory bandwidth or limited RAM capacity.
Multi-Element Support
Accepts various parasitic representations including resistors (R), capacitors (RC, RCC), inductors (RLC), and mutual inductance (RLCK).
Simulation Time Acceleration
Decreases analysis time from days to minutes by creating a smaller, more efficient equivalent circuit.
Parallel Processing
Uses a massively parallel design flow to efficiently absorb and utilize increased computational resources.
Technology Node Independence
Operates on extracted netlists from any technology node, making it compatible with all semiconductor manufacturing processes.
EDA Tool Compatibility
Produces output files in standard formats readable by popular simulators like Cadence Virtuoso and Multisim.
Conditioning Enhancement
Improves the mathematical properties of the output netlist to speed up iterative solvers in circuit simulators.
Post-Layout Integration
Fits seamlessly into existing analog, RF, and digital design flows after the parasitic extraction phase.
Wideband Support
Maintains signal integrity and accuracy across a broad frequency spectrum, ranging from DC to terahertz.
Realizable Netlist Generation
Ensures that the final output is a physical netlist that can be simulated without numerical stability issues.

Pricing

Free trial
Free version
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Countries & Languages

Global
Countries served
1
Interface languages
1
Billing currencies

Interface languages

English

Billing currencies

🇺🇸USD

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